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wide dynamic range , high speed , digitally controlled vga data sheet ADL5201 rev. b document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringeme nts of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2011 - 2013 analog devices, inc. all rights reserved. technical support www.analog.com features ?11.5 db to + 20 db gain r ange 0.5 db 0.1 db step size 150 ? differential input and output 7.5 db noise figure at maximum gain oip3 > 50 dbm at 200 mhz ?3 db upper frequency bandwidth of 700 mhz multiple control interface options parallel 6 - bit control interface (with latch) serial peripheral interface (spi) (with fast attack) gain up/down mode wide input dynamic range low p ower mode option power - down control single 5 v supply operation 24 -l ead , 4 mm 4 mm lfcsp package a pplications differential adc drivers high if sampling receivers high output power if amplification instrumentation functional block dia gram +20db ADL5201 spi with fa, parallel with latch, up/down interface vpos gnd pwup 0db to 31.5db vin+ mode0, mode1 vin? pm vout+ vout? 09388-001 150? 150? logic figure 1. general description the ADL5201 is a digitally controlled, variable gain , wide band - width amplifier that provides precise gain control, high ip3 , and low noise figure. the excellent distortion performance and high signal bandwidt h make the ADL5201 an excellent gain control device for a variety of receiver applications. the ADL5201 also incorporates a low power mode option that lowers the supply current . for wide input dynamic range applications, the ADL5201 pro vides a broad 31.5 db gain range with 0 .5 db resolution. the gain is adjustable through multiple gain control interface options: parallel, serial peripheral i nterface, and up/down. i ncorporating proprietary distortion cancellation techniques, the ADL5201 achieves a n output ip3 of greater than 47 dbm at frequencies approaching 2 00 mhz for most gain settings. the ADL5201 is powered on by applying the appropriate logic leve l to the pwup pin. the quiescent current of the ADL5201 is typically 80 ma in low power mode . when configured in high performance mode for more demanding applications, the quiescent current is 110 ma . when powered down, the ADL5201 consumes less than 7 ma and offers excellent input - to - output isolation. the gain setting is preserved during power - down. fabricated on an analog devices, inc., high speed sige process , the ADL5201 provides precise gain adjustment capabilities with good distortion performance and low phase error. the ADL5201 amplifier comes in a compact, thermally enhanced , 24 -lead, 4 mm 4 mm lfcsp package and operates over the temperature range of ? 40c to +85 c.
ADL5201 data sheet re v. b | page 2 of 28 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing diagrams .......................................................................... 4 absolute maximum ratings ............................................................ 5 esd caution .................................................................................. 5 pin configuration and function descriptions ............................. 6 typical performance characteristics ............................................. 7 characterization and test circuits ............................................... 14 theory of operation ...................................................................... 15 digital interface overview ........................................................ 15 parallel digital interface ............................................................ 15 serial peripheral interface (spi) ............................................... 15 up/down interface .................................................................... 15 logic timing ............................................................................... 16 circuit description ......................................................................... 17 basic structure ............................................................................ 17 input system ............................................................................... 17 output amplifier ........................................................................ 17 gain control ............................................................................... 17 applications information .............................................................. 18 basic connections ...................................................................... 18 adc driving ............................................................................... 18 layout considerations ............................................................... 20 evaluation board ............................................................................ 21 evaluation board control software ......................................... 21 schematics and artwork ........................................................... 22 evaluation board configuration options ............................... 24 outline dimensions ....................................................................... 26 ordering guide .......................................................................... 26 revision history 9 /1 3 rev . a to rev . b change d logic pins absolute maximum rating from 3.6 v t o ?0. 3 v to +3.6 v (not to exceed |vpos ? 0.5 v| at any time) .... 5 12 /12 rev . 0 to rev . a changes to layout consideration section .................................. 20 updated outline dimensions ....................................................... 26 10/11 revision 0: initial version
data sheet ADL5201 rev. b | page 3 of 28 specifications v s = 5 v, t a = 25c, r s = r l = 150 ? at 100 mh z, high performance mode , 2 v p - p differential output , unless otherwise noted. table 1 . parameter test conditions/comments min typ max unit dynamic performance ?3 db bandwidth v out < 2 v p - p (5.2 dbm) 700 mhz slew rate 5.5 v/ns input return loss ( s11 ) 100 mhz ? 18.73 db output return loss ( s22 ) 100 mhz ? 18.8 db input stage vin + and vin? pins maximum input swing (differential) gain code = 111111 10.8 v p -p differential input resistance 150 ? common -mo de input voltage 1.5 v cmrr gain code = 000000 51.44 db gain maximum voltage gain gain code = 000000 20 db minimum voltage gain gain code = 111111 ? 11.5 db gain step size 0.5 db gain flatness 30 mhz < f c < 200 mhz 0.285 db gain temperature sensitivity gain code = 000000 0.0089 db/ c gain step response for v in = 0.2 v, gain code = 111111 to 000000 15 ns gain conformance error over 10 db gain range 0.03 db phase conformance error over 10 db gain range 1.0 degrees out put stage v out+ and v out ? pins output voltage swing at p1db, gain code = 000000 10 v p -p differential output resistance differential 150 ? noise/harmonic performance 46 mhz gain code = 000000, high performance mode second harmonic v out = 2 v p -p ? 86 db c third harmonic v out = 2 v p -p ? 104 dbc output ip3 (oip3) v out = 2 v p - p composite 50 dbm 70 mhz gain code = 000000, high performance mode second harmonic v out = 2 v p -p ? 91 dbc third harmonic v out = 2 v p -p ? 103 dbc output ip3 (oi p3) v out = 2 v p - p composite 51 dbm 140 mhz gain code = 000000, high performance mode noise figure 7.5 db second harmonic v out = 2 v p -p ? 89 dbc third harmonic v out = 2 v p -p ? 97 dbc output ip3 (oip3) v out = 2 v p - p composite 51 dbm output 1 db compression point (oip1 db) 19.8 db m 300 mhz gain c ode = 000000, high performance mode second harmonic v out = 2 v p -p ? 85 dbc third harmonic v out = 2 v p -p ? 90 dbc output ip3 (oip3) v out = 2 v p - p composite 50 dbm
ADL5201 data sheet rev. b | page 4 of 28 parameter test conditions/comments min typ max unit power-up interface pwup pin power-up threshold minimum voltage to enable the device 1.4 v maximum voltage to enable the device 3.3 v pwup input bias current 1 a gain control interface v ih minimum/maximum voltage for a logic high 1.4 3.3 v v il maximum voltage for a logic low 0.8 maximum input bias current 1 a spi timing latch, sclk, sdio, data pins f sclk 1/t sclk 20 mhz t dh data hold time 5 ns t ds data setup time 5 ns t pw sclk high pulse width 5 ns power interface supply voltage 4.5 5.5 v quiescent current high performance mode 110 ma 85c 120 ma low power mode 80 ma 85c 95 ma power-down current pwup low 7 ma timing diagrams sclk cs sdio t sclk t ds t ds t dh t pw t dh dnc dnc dnc dnc dnc dnc dnc r/w fa1 fa0 d5 d4 d3 d2 d1 d0 09388-002 figure 2. spi interface read/write mode timing diagram dn up t ds t ds t pw t ds t dh updn_dat updn_clk 09388-003 reset figure 3. up/down mode timing diagram latch a5 to a0 t dh 09388-104 figure 4. parallel mode timing diagram
data sheet ADL5201 rev. b | page 5 of 28 absolute maximum rat ings table 2 . parameter rating supply voltage, v pos 5.5 v pwup, a0 to a 5, mode0, mode 1, pm, l atch ? 0.3 v to + 3.6 v (not to exceed |vpos ? 0.5 v| at any time) input voltage, v in+ and v in ? +3.6 v to ? 1.2 v internal power dissipation 676.5 mw ja (exposed paddle soldered d own) 37.16 c/w jc (a t expo sed p addle) 2.29 c/w maximum junction temperature 140 c operating temperature range C 40 c to +85 c storage temperature range C 65 c to +150 c lead temperature (soldering , 60 sec) 240 c stresses above those listed under absolute maximum ratings may c ause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum ratin g conditions for extended periods may affect device reliability. esd caution
ADL5201 data sheet rev. b | page 6 of 28 pin configuration and fu nction descriptions notes 1. the exposed paddle (ep) must be connected to a low impedance ground pad. 09388-004 2 1 3 4 5 6 1 8 1 7 1 6 1 5 1 4 1 3 m o d e 0 m o d e 1 g n d v i n ? v i n + g n d l a t c h v o u t + v o u t ? v o u t + v o u t ? v p o s 8 9 1 0 1 1 7 s c l k / a 4 g s 1 / c s / a 3 g s 0 / f a / a 2 u p d n _ c l k / a 1 1 2 u p d n _ d a t / a 0 s d i o / a 5 2 0 1 9 2 1 p m p w u p v p o s 2 2 v p o s 2 3 v p o s 2 4 v p o s ADL5201 top view (not to scale) figure 5. pin configuration table 3. pin function descriptions pin no. mnemonic description 1, 4, ep gnd ground. the exposed paddle (ep) must be connected to a low impedance ground pad. 2 vin+ positive input. 3 vin? negative input. 5 mode1 msb for mode control. with the mode0 pin, selects parallel, spi, or up/down interface mode. 6 mode0 lsb for mode control. with the mode1 pin, selects parallel, spi, or up/down interface mode. 7 sdio/a5 serial data input/output (sdio). when cs is pulled low, sdio is used for reading and writing to the spi port. bit 5 for parallel gain control interface (a5). 8 sclk/a4 serial clock input in spi mode (sclk). bit 4 for parallel gain control interface (a4). 9 gs1/cs /a3 msb for gain step size control in up/down mode (gs1). spi interface select (cs ). when serial mode is enabled, a logic low (0 v cs 0.8 v) enables the spi interface. bit 3 for parallel gain control interface (a3). 10 gs0/fa/a2 lsb for gain step size control in up/down mode (gs0). fast attack (fa). in serial mode, a logic high (1.4 v fa 3.3 v) attenuates according to the fa setting in the spi word. bit 2 for parallel gain control interface (a2). 11 updn_clk/a1 clock interface for up/down function (updn_clk). bit 1 for parallel gain control interface (a1). 12 updn_dat/a0 data pin for up/down function (updn_dat). bit 0 for parallel gain control interface (a0). 13 latch a logic low (0 v latch 0.8 v) allows gain changes. a logic high (1.4 v latch 3.3 v) disallows gain changes. 14, 16 vout+ positive output. 15, 17 vout? negative output. 18, 21, 22, 23, 24 vpos positive power supply. 19 pwup power-up pin. a logic high (1.4 v pwup 3.3 v) enables the part. 20 pm performance mode. a logic low (0 v pm 0.8 v) enables high performance mode. a logic high (1.4 v pm 3.3 v) enables low power mode.
data sheet ADL5201 rev. b | page 7 of 28 typical performance characteristics v s = 5 v, t a = 25c, r s = r l = 150 ? at 200 mhz, high performance mode , 2 v p - p differential output , unless otherwise noted. ?15 ?10 ?5 0 5 10 15 20 25 0 10 20 30 40 50 60 70 gain (db) gain code 46mhz 140mhz 300mhz 09388-005 figure 6. g ain vs. gain code at 46 mhz, 140 mhz, and 300 mhz 0 5 10 15 20 25 30 35 40 45 ?15 ?10 ?5 0 5 10 15 20 25 noise figure (db) programmed gain (db) 09388-006 figure 7. noise figure vs. programmed gain at 140 mhz 0 5 10 15 20 25 ?15 ?10 ?5 0 5 10 15 20 25 op1db (dbm) programmed gain (db) 09388-007 input max ratings boundary figure 8. o p1db vs. programmed gain at 140 mhz ?20 ?15 ?10 ?5 0 5 10 15 20 25 10 100 1000 gain (db) frequenc y (mhz) 4db 3db 2db 1db 0db ?1db ?2db ?3db ?4db ?5db ?6db ?7db ?8db ?9db ?10db ?11db 20db 19db 18db 17db 16db 15db 14db 13db 12db 11db 10db 9db 8db 7db 6db 5db 09388-008 figure 9. gain vs. frequency response (every 1 db step) 0 5 10 15 20 25 30 35 40 45 0 100 200 300 400 500 600 noise figure (db) frequenc y (mhz) mid gain (+5db) max gain (+20db) min gain (?11.5db) 09388-009 t a = ?40c t a = +25c t a = +85c figure 10 . no ise figure vs. frequency at max, mid, and min gain output s frequenc y (mhz) 0 4 8 12 16 20 2 6 10 14 18 0 50 100 150 200 250 300 350 400 op1db (dbm) 09388-010 t a = ?40c t a = +25c t a = +85c figure 11 . o p1db vs. frequency at maximum gain, three temperatures
ADL5201 data sheet re v. b | page 8 of 28 30 35 40 45 50 55 60 0 50 100 150 200 250 300 350 400 oip3 (dbm) frequenc y (mhz) ?11.5db 0db +10db +20db 09388-0 11 figure 12 . output third - order intercept vs. frequency at four gain codes frequenc y (mhz) 30 35 40 45 50 55 60 0 50 100 150 200 250 300 350 400 oip3 (dbm) t a = ?40c t a = +25c t a = +85c 09388-012 figure 13 . output third - order intercept vs. frequency , three temperatures at 2 v p- p composite ?120 ?1 10 ?100 ?90 ?80 ?70 ?60 ?15 ?10 ?5 0 5 10 15 20 25 imd3 (dbc) programmed gain (db) 46mhz 140mhz 300mhz 09388-013 figure 14 . two - tone ou tput imd 3 vs. programmed gain at 46 mhz, 140 mhz, and 300 mhz 20 25 30 35 40 45 50 55 60 ?4 ?3 ?2 ?1 0 1 2 3 4 5 6 oip3 (dbm) p out (dbm) ?11.5db 0db +10db +20db 09388-014 input max ratings boundary figure 15 . output third - order intercept vs. power at four gain codes, frequency = 140 mhz at 2 v p - p composite 30 35 40 45 50 55 60 ?4 ?3 ?2 ?1 0 1 2 3 4 5 6 oip3 (dbm) p out (dbm) t a = ?40c t a = +25c t a = +85c 09388-015 figure 16 . output third - order intercept vs. power, frequency = 140 mhz , three temperatures ?120 ?1 10 ?100 ?90 ?80 ?70 ?60 0 50 100 150 200 250 300 350 400 imd3 (dbc) frequenc y (mhz) t a = ?40c t a = +25c t a = +85c 09388-016 figure 17 . two - tone output imd 3 vs. frequency , three temperatures
data sheet ADL5201 rev. b | page 9 of 28 ?120 ?1 10 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?150 ?140 ?130 ?120 ?1 10 ?100 ?90 ?80 ?70 ?60 ?50 0 50 100 150 200 250 300 350 harmonic dis t ortion hd3 (dbc) harmonic dis t ortion hd2 (dbc) frequenc y (mhz) ?11.5db 0db +10db +20db 09388-017 figure 18 . harmonic distortion vs. frequency at four gain codes ?120 ?1 10 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?140 ?130 ?120 ?1 10 ?100 ?90 ?80 ?70 ?60 0 50 100 150 200 250 300 350 harmonic dis t ortion hd3 (dbc) harmonic dis t ortion hd2 (dbc) frequenc y (mhz) t a = ?40c t a = +25c t a = +85c 09388-018 figure 19 . harmonic distortion vs. frequency, three temperatures 0 5 10 15 20 25 ?15 ?10 ?5 0 5 10 15 20 25 op1db (dbm) programmed gain (db) 09388-019 input max ratings boundary figure 20 . o p1db vs. programmed gain at 140 mhz, low power mode ?120 ?1 10 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?140 ?130 ?120 ?1 10 ?100 ?90 ?80 ?70 ?60 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 6 harmonic dis t ortion hd3 (dbc) harmonic dis t ortion hd2 (dbc) p out (dbm) ?11.5db 0db +10db +20db 09388-020 figure 21 . harmonic di stortion vs. power at four gain codes , frequency = 140 mhz ?120 ?1 10 ?100 ?90 ?80 ?70 ?60 ?140 ?130 ?120 ?1 10 ?100 ?90 ?80 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 6 harmonic dis t ortion hd3 (dbc) harmonic dis t ortion hd2 (dbc) p out (dbm) t a = ?40c t a = +25c t a = +85c 09388-021 figure 22 . harmonic distortion vs. power, frequency = 140 mhz, three temperatures frequenc y (mhz) 0 50 100 150 200 250 300 350 400 op1db (dbm) 09388-022 0 4 8 12 16 20 2 6 10 14 18 t a = ?40c t a = +25c t a = +85c figure 23 . o p1db vs. frequency at maximum gain, three temperatures, low p ower mode
ADL5201 data sheet re v. b | page 10 of 28 30 35 40 45 50 55 60 0 50 100 150 200 250 300 350 400 oip3 (dbm) frequenc y (mhz) ?11.5db 0db +10db +20db 09388-023 figure 24 . output third - order intercept vs. frequency at four gain codes, low power mode at 2 v p - p composite frequenc y (mhz) 30 35 40 45 50 55 60 0 50 100 150 200 250 300 350 400 oip3 (dbm) t a = ?40c t a = +25c t a = +85c 09388-024 figure 25 . output third - order intercept vs. frequency, three temperatures, low power mode ?120 ?1 10 ?100 ?90 ?80 ?70 ?60 ?15 ?10 ?5 0 5 10 15 20 25 imd3 (dbc) programmed gain (db) 46mhz 140mhz 300mhz 09388-025 figure 26 . two - tone output imd 3 vs. programmed gain at 46 mhz, 140 mhz, and 300 mhz; low power mode 20 25 30 35 40 45 50 55 60 ?4 ?3 ?2 ?1 0 1 2 3 4 5 6 oip3 (dbm) p out (dbm) ?11.5db 0db +10db +20db 09388-026 input max ratings boundary figure 27 . output third - order intercept vs. power at four gain codes, frequency = 140 mhz, low power mode 30 35 40 45 50 55 60 ?4 ?3 ?2 ?1 0 1 2 3 4 5 6 oip3 (dbm) p out (dbm) t a = ?40c t a = +25c t a = +85c 09388-027 figure 28 . output third - order intercept vs. power, three temperatures, low power mode at 2 v p- p composite ?120 ?1 10 ?100 ?90 ?80 ?70 ?60 0 50 100 150 200 250 300 350 400 imd3 (dbc) frequenc y (mhz) t a = ?40c t a = +25c t a = +85c 09388-028 figure 29 . two - tone output imd 3 vs. frequency , three temperatures, lo w power mode
data sheet ADL5201 rev. b | page 11 of 28 ?120 ?1 10 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?150 ?140 ?130 ?120 ?1 10 ?100 ?90 ?80 ?70 ?60 ?50 0 50 100 150 200 250 300 350 harmonic dis t ortion hd3 (dbc) harmonic dis t ortion hd2 (dbc) frequenc y (mhz) ?11.5db 0db +10db +20db 09388-029 figure 30 . harmonic distortion vs. frequency at four gain code s, low power mode 0 50 100 150 200 250 300 350 harmonic dis t ortion hd3 (dbc) harmonic dis t ortion hd2 (dbc) frequenc y (mhz) t a = ?40c t a = +25c t a = +85c ?120 ?1 10 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?150 ?140 ?130 ?120 ?1 10 ?100 ?90 ?80 ?70 ?60 ?50 09388-030 figure 31 . harmonic distortion vs. frequency, three temperatures, low power mode ch1 200mv/div ch4 1mv/div volt age time ( 10ns/div) 09388-031 figure 32 . enable time domain response ?120 ?1 10 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?140 ?130 ?120 ?1 10 ?100 ?90 ?80 ?70 ?60 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 6 harmonic dis t ortion hd3 (dbc) harmonic dis t ortion hd2 (dbc) p out (dbm) ?11.5db 0db +10db +20db 09388-032 figure 33 . harmonic distortion vs. power at four gain code s, frequency = 140 mhz, low power mode ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 6 harmonic dis t ortion hd3 (dbc) harmonic dis t ortion hd2 (dbc) p out (dbm) ?1 10 ?100 ?90 ?80 ?70 ?60 ?50 ?130 ?120 ?1 10 ?100 ?90 ?80 ?70 t a = ?40c t a = +25c t a = +85c 09388-033 figure 34 . harmonic distortion vs. power, frequency = 14 0 mhz, three temperatures, low power mode ch1 200mv/div ch4 1v/div volt age time ( 10ns/div) 09388-034 figure 35 . disable time domain response
ADL5201 data sheet re v. b | page 12 of 28 ch2 500mv/div ch3 50mv/div volt age time ( 10ns/div) 09388-035 figure 36 . gain step time domain response s1 1 phase (degrees) s1 1 magnitude (db) frequenc y (mhz) ?200 ?150 ?100 ?50 0 50 100 150 200 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 100 1000 magnitude max gain magnitude min gain phase max gain phase min gain 09388-036 figure 37 . s11 magnitude and phase vs. freque ncy ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 ?15 ?10 ?5 0 5 10 15 20 25 gain error (db) programmed gain (db) 09388-037 figure 38 . gain step error, frequency = 140 mhz 0pf 5.6pf differential input 200mv/div volt age time ( 1ns/div) 09388-038 figure 39 . large signal pulse response , 0 pf and 5.6 pf, 2 v p - p composite s22 phase (degrees) s22 magnitude (db) frequenc y (mhz) ?200 ?150 ?100 ?50 0 50 100 10 100 1000 magnitude max gain magnitude min gain phase max gain phase min gain 09388-039 150 200 250 300 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 figure 40 . s22 magnitude and phase vs. fre quency ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 100 1000 reverse isol a tion (db) frequenc y (mhz) 09388-041 figure 41 . reverse isolation vs. frequency
data sheet ADL5201 rev. b | page 13 of 28 0 0.2 0.4 0.6 0.8 1.0 10 100 1000 grou p del ay (ns) frequenc y (mh z) max mid min 09388-042 figure 42 . group delay vs. frequency at max, mid, and min gain outputs 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 10 20 30 40 50 60 70 phase v ari a tion (degrees) gain code 350mhz 300mhz 250mhz 200mhz 150mhz 100mhz 50mhz 09388-043 figure 43 . phase variation vs. gain code ?60 ?50 ?40 ?30 ?20 ?10 0 10 100 1000 reverse isol a tion (db) frequenc y (mhz) 09388-044 figure 44 . disable -state reverse isolation vs. frequency 0 10 20 30 40 50 60 10 100 1000 common-mode rejection r a tio, cmrr (db) frequenc y (mhz) 09388-045 figure 45 . common - mode rejection ratio vs. frequency
ADL5201 data sheet re v. b | page 14 of 28 characterization and test circuit s 0.1f 0.1f l1 1h l2 1h 0.1f c1 c3 0.1f c2 c4 +5v 6 a0 to a5 ac 50? traces 50? traces 50? 50? 50? 50? ac ADL5201 09388-046 figure 46 . test circui t for s - parameters on dedicated 50 ? differential -to- differential board c1 0.1f c2 0.1f tc3-1t t1 l1 1h l2 1h c3 0.1f c4 0.1f r1 62? r2 62? r4 25? r3 25? etc1-1-13 t2 50? pad loss = 11db +5v 6 a0 to a5 50? ac ADL5201 09388-047 figure 47 . test circuit for distortion, gain, and noise 09388-048 figure 48 . differential -to- diffe rential characterization board
data sheet ADL5201 rev. b | page 15 of 28 theory of operation digital interface overview the ADL5201 dvga has three digital gain control options: parallel control interface, serial peripheral interface, and gain up/down interface. the desired gain control option is selected via two control pins, mode0 and mode1 (see table 4 for the truth table for the mode control pins). the gain code is in 6-bit binary format. a voltage from 1.4 v to 3.3 v is required for a logic high. two pins are common to all gain control options: pm and pwup. pm allows the user to choose operation in low power mode or high performance mode. pwup is the power-up pin. physical pins are shared among the three interfaces, resulting in as many as three different functions per digital pin (see table 3). table 4. digital control interface selection truth table mode1 mode0 interface 0 0 parallel control 0 1 serial peripheral (spi) 1 0 up/down 1 1 up/down parallel digital interface the parallel digital interface uses six binary bits (bits[a5:a0]) and a latch pin (latch). the latch pin controls whether the input data latch is transparent or latched. in transparent mode, the gain changes as the input gain control bits change. in latched mode, gain is determined by the latched gain setting and does not change with the input gain control bits. serial peripheral interface (spi) the spi uses three pins: sdio, sclk, and cs . the spi data register consists of two bytes: six gain control bits, two attenu- ation step size address bits, one read/write bit, and seven dont care bits. sdio is the serial data input and output pin. the sclk pin is the serial clock, and cs is the channel select pin. data read/write do not care (7 bits) fast attack attenuation step size address gain control 09388-050 d0 d1 d2 d3 d4 d5 fa0 fa1 msb lsb msb r/w dnc dnc dnc dnc dnc dnc dnc figure 49. 16-bit spi register to write to the spi register, cs must be pulled low and 16 clock pulses must be applied to sclk. to read the spi register value, the r/w bit must be set high, cs must be pulled low, and the part must be clocked. after the register is read out during the next 16 clock cycles, the spi is automatically placed in write mode. fast attack the fast attack feature, accessible via the spi, allows the gain to be reduced from its present gain setting by a predetermined step size. four different attenuation step sizes are available. the truth table for fast attack is shown in table 5. table 5. spi 2-bit attenuation step size truth table fa1 fa0 step size (db) 0 0 2 0 1 4 1 0 8 1 1 16 spi fast attack mode is controlled by the fa pin. a logic high on the fa pin results in an attenuation that is selected by bits[fa1:fa0] in the spi register. up/down interface the gs1 and gs0 pins control the up/down gain step function. gain is increased by a clock pulse on the updn_clk pin (rising and falling edges) when the updn_dat pin is high. gain is decreased by a clock pulse on the updn_clk pin when the updn_dat pin is low. dn up reset updn_dat updn_clk 09388-049 figure 50. up/down timing reset is detected by a rising edge latching data having one polarity, with the falling edge latching the opposite polarity. reset results in a minimum binary gain code of 111111. the truth table for the gain step function is shown in table 6. the step size is selectable using the gs1 and gs0 pins. the gain is limited by the top and bottom of the control range. table 6. gain step size control truth table gs1 gs0 step size (db) 0 0 0.5 0 1 1 1 0 2 1 1 4
ADL5201 data sheet rev. b | page 16 of 28 truth table table 7. gain code vs. voltage gain lookup table 6-bit binary gain code voltage gain (db) 6-bit binary gain code voltage gain (db) 000000 20 100000 4 000001 19.5 100001 3.5 000010 19 100010 3 000011 18.5 100011 2.5 000100 18 100100 2 000101 17.5 100101 1.5 000110 17 100110 1 000111 16.5 100111 0.5 001000 16 101000 0 001001 15.5 101001 ?0.5 001010 15 101010 ?1 001011 14.5 101011 ?1.5 001100 14 101100 ?2 001101 13.5 101101 ?2.5 001110 13 101110 ?3 001111 12.5 101111 ?3.5 010000 12 110000 ?4 010001 11.5 110001 ?4.5 010010 11 110010 ?5 010011 10.5 110011 ?5.5 010100 10 110100 ?6 010101 9.5 110101 ?6.5 010110 9 110110 ?7 010111 8.5 110111 ?7.5 011000 8 111000 ?8 011001 7.5 111001 ?8.5 011010 7 111010 ?9 011011 6.5 111011 ?9.5 011100 6 111100 ?10 011101 5.5 111101 ?10.5 011110 5 111110 ?11 011111 4.5 111111 ?11.5 logic timing to write to the ADL5201 , refer to the timing shown in figure 51. the write mode uses a 16-bit serial word on the sdio pin. the r/w bit of the word must be low to write bits[d5:d0], which are the binary weighted codes for the attenuation level (0 = minimum attenuation, 63 = maximum attenuation). the fa0 and fa1 bits control the fast attack step size. the dnc bits are nonfunctional, do not care bits. reading the ADL5201 spi register requires the following two steps: 1. set the r/w bit high using a 16-bit word and the timing shown in figure 51. all other bits are ignored when the r/w bit is high. 2. the sdio is used as an output during the next sequence. the written pattern is serially clocked out on sdio using 16 clocks and the timing shown in figure 51. the r/w bit automatically returns low to the write state following the read sequence. sclk cs sdio t sclk t ds t ds t dh t pw t dh dnc dnc dnc dnc dnc dnc dnc r/w fa1 fa0 d5 d4 d3 d2 d1 d0 09388-151 figure 51. spi interface read/write mode timing diagram
data sheet ADL5201 rev. b | page 17 of 28 circuit description basic structure the ADL5201 is a differential variable gain amplifier (vga) consisting of a 150 digitally controlled p assive attenuator followed by a highly linear transconductance amplifier with feedback. attenuator logic ref vin+ vin? vout+ vout? digital inputs parallel, spi, fast attack up/down ADL5201 g m amp 09388-051 figure 52 . simplified schematic input system the dc voltage level at the input of the amplifier is set by an independent internal voltage reference circuit to approximately 1.6 v. the reference is not accessible and cannot be adjusted. the amplifier can be powered down by pulling the pwup pin low . in power - down mode, the total current is reduced to 7 ma (typical). the dc level at the input remains at approximately 1.6 v, regardless of the state of the pwup pin. output amplifier gain of the output amplifier is set to be 22 db when driving a 150 load. the input and output resistance of this amplifier is set to 150 in matched condition. if the load or the source resistance is not equal to 150 , the following equations can be used to determine the resulting gai n and input/ output resistances . voltage gain = a v = 0.09 (2000)// r l r in = (2000 + r l )/(1 + 0.09 r l ) s21 (gain) = 2 r in /( r in + r s ) a v r out = (2000 + r s )/(1 + 0.09 r s ) note that the at maximum attenuation setting, r s , as seen by the output amplifier , is the output resistance of the attenuator , which is 150 ? . however, at the minimum attenuation setting, r s is the source resistance that is conne cted to the input of the part. the dc current to the outputs of each amplifier is supplied through two external chokes. the inductance of the chokes and the resistance of the load, in parallel with the output resistance of the device, add a low frequency pole to the response. the para - sitic capacitance of the chokes adds to the output capacitance of the part. this total capacitance, in parallel with the load and output resistance, sets the high frequency pole of the device. generally, the larger the inductance of the choke, the higher its parasitic capacitance. therefore, this trade - off must be considered when the value and type of the choke are selected . for an operatio n frequency of 15 mhz to 700 mhz driving a 150 load, 1 h chokes with an srf of 160 mhz or higher are recommended (such as the 0805ls - 102xjbb from coilcraft). if higher value chokes are used, a 4 mhz zero, due to the internal ac - coupled feedback, causes an increase in s21 of up to 6 db at frequencies below 4 mhz. the supply current of the amplifier consists of about 35 ma through the v pos pin and 50 ma through the two chokes combined. the latter increases with temperature at approximately 2.5 ma per 10c . the total choke current increases to 75 ma for high performance mode. the amplifier has two output pins for each polarity, and they are oriented in an alternating fashion. when designing the board, care should be taken to minimize the parasitic capacitan ce due to the routing that connects the corresponding outputs together. to minimize the parasitic capacitance, a good practice is to avoid any ground or power plane under this routing region and under the chokes. gain control the gain can be adjusted usin g the parallel control interface, the serial peripheral interface , or th e gain up/down interface. in g ene ral , the gain step size is 0.5 db, but larger sizes can be programm ed using the various interfaces, as described in the digita l interface overview section. the amplifier has a maximum gain of + 20 db (code 0) to ? 11.5 db (code 63). the noise figure of the amplifier is approximately 7.5 db at the maximum gain setting , and it increases as the gain is reduced. the increase in noise figure is equal to the reduction in gain. the linearity of the part , measured at the output , is first - order independent of the gain setting. from ? 4 db to + 20 db gain, the oip3 is approximately 50 dbm into a 150 load at 200 mhz (0 dbm per tone). at gain settings below ? 4 db, the oip3 drops to approximately 40 dbm.
ADL5201 data sheet rev. b | page 18 of 28 applications information basic connections figure 53 shows the basic connections for operating the ADL5201 . a voltage between 4.5 v and 5.5 v should be applied to the vpos pins. each supply pin should be decoupled with at least one low inductance, surface-mount ceramic capacitor of 0.1 f, placed as close as possible to the device. the outputs of the ADL5201 must be pulled up to the positive supply with 1 h rf chokes. the differential outputs are biased to the positive supply and require ac coupling capacitors, preferably 0.1 f. similarly, the input pins are at bias voltages of about 1.6 v above ground and should be ac-coupled, as well. the ac coupling capacitors and the rf chokes are the principle limitations for operation at low frequencies. the digital pins (mode control pins, associated spi and parallel gain control pins, pm, and pwup) operate on a voltage of 3.3 v. to enable the ADL5201 , the pwup pin must be pulled high (1.4 v pwup 3.3 v). taking pwup low puts the ADL5201 in sleep mode, reducing current consumption to approximately 7 ma at ambient temperature. adc driving the ADL5201 is a highly linear, variable gain amplifier that is optimized for adc interfacing. the output imds and noise floor remain constant throughout the 31.5 db gain range. this is a valuable feature in a variable gain receiver, where it is desirable to maintain a constant instantaneous dynamic range as the receiver range is modified. the output noise is 15 nv/hz, which is compatible with 14- or 16-bit adcs. the two-tone imds are usually greater than ?100 db for ?1 dbm into 150 or 2 v p-p output. the 150 output impedance makes the task of designing a filter for the high input impedance adcs more straightforward. gain control interface 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f r s 2 r s 2 ac balanced source r l balanced load 1h 1h 0.1f 0.1f 10f +v pos 24 23 22 21 20 19 18 17 16 15 14 13 12 7891011 1 2 3 4 5 6 mode0 ADL5201 3.3v 3.3v gain mode interface m o d e 0 m o d e 1 g n d v i n ? v i n + g n d l a t c h v o u t + v o u t ? v o u t + v o u t ? v p o s s c l k / a 4 g s 1 / c s / a 3 g s 0 / f a / a 2 u p d n _ c l k / a 1 u p d n _ d a t / a 0 s d i o / a 5 p m p w u p v p o s v p o s v p o s v p o s 09388-052 figure 53. basic connections
data sheet ADL5201 rev. b | page 19 of 28 50? ac 1:3 75? 75? 33? 33? 1h 5v 1h 5v v ref v ref 5v 0.1 f 0.1 f 0.1 f 47nh 47nh 0.1 f digital interface ADL5201 14pf ad9467 09388-053 figure 54 . wideband adc interfacing example featuring t he ADL5201 and the ad9467 figure 54 shows the ADL5201 driving a two - pole, 100 mhz, low - pass filter into the ad9467 . the ad9467 is a 16 - bit, 200 msps to 250 msps adc with a buffered wide band inpu t that presents a 530 ? d ifferential input impedance and requires a 2 v or 2.5 v input swing to reach full scale. for opti mum performance, the ADL5201 should be driven differentially , using an impedance transfor mer or input balun. ?12 ?11 ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 0 20 40 60 80 100 120 140 160 180 200 frequenc y (mhz) insertion loss (db) 09388-054 figure 55 . measured frequency response of the wideband adc interface shown in figure 54 figure 54 uses a 1:3 impedance tra nsformer to provide the 150 ? in put impedance of the ADL5201 with a matched input. the outputs of the ADL5201 are biased through the two 1 h inductors , and the t wo 0.1 f capacitors on the outputs decouple the 5 v inducto r voltage from the input common - mode voltage of the ad9467 . the two 75 ? resistors provide the 150 ? load to the ADL5201 , whose gain is load depende nt. the 47 nh induc - tors and 14 pf capacitor constitute the ( 100 mhz ? 1 db ) low - pass filter. the two 33 ? isolation resistors suppress any switching cur rents from the adc input sample - an d- hold circuitry. the circuit depicted in figure 54 provides variable gain, isolation, filtering , and source matching for the ad9467 . by u sing this circuit with the ADL5201 in a gain of 20 db (maximum gain) , an snr of 68 db and an sfdr performance of 88 dbc are achieved at 100 mhz , as shown in figure 56. 0 ?15 ?30 ?45 ?60 ?75 ?90 ?105 ?120 ?150 ?135 0 15 30 45 60 75 90 105 120 amplitude (dbfs) frequency (mhz) snr = 68db sfdr = 88dbc noise floor = ?114dbfs fund = ?1.05dbfs second = ?94.7dbc third = ?88.75dbc 5 + 6 4 3 2 09388-055 figure 56 . m easured single - tone performance of the circuit shown in figure 54 for a 100 mhz input signal the two - tone 100 mhz imds of two 1 v p - p signals have an sfdr of greater than 91 dbc , as shown in figure 57. 0 ?15 ?30 ?45 ?60 ?75 ?90 ?105 ?120 ?150 ?135 0 15 30 45 60 75 90 105 120 amplitude (dbfs) frequency (mhz) fund1 = ?6.682dbfs fund2 = ?7.096dbfs 2f1 ? f2 = ?93.2dbfs 2f2 ? f1 = ?92.58dbc noise floor = ?115.3dbfs f2 ? f1 + f1 + f2 2f2 + f1 2f1 ? f2 2f2 ? f1 2f1 + f2 09388-056 figure 57 . measured two - tone performance of the circuit shown in figure 54 for a 100 mhz input signal
ADL5201 data sheet re v. b | page 20 of 28 an alternative narrow - band approach is presented in figure 58. by designing a narrow band - pass antialiasing filter between the ADL5201 a nd the target adc, the output noise of the ADL5201 outside the intended nyquist zon e can be attenuated, helping to preserve the available snr of the adc. in gene ral, the snr improves by several decibels (db) when a reasonable order antialiasing filter is included . in this example, a low loss 1:3 input tran sformer is used to match the 150 balanced input of the ADL5201 to a 50 unbal anced source, resulting in minimum insertion loss at the input. figure 58 shows the ADL5201 optimized for driving some of the popular unbuffered analog devices adcs: the ad9246 , ad9640 , and ad6655 . table 8 includes antialiasing filter component recommendations for popular if sampling center frequencies. inductor l5 wor ks in parallel with the on - chip adc input capacitance and a portion of the capaci tance presented by c4 to form a resonant tank circuit. the resonant tank helps to ensure that the adc input looks like a real resistance at the target center frequency. in ad dition , the l 6 inductor shorts the adc inputs at dc, which introduces a zero into the transfer function. t he ac coupling capacitors and the bias chokes introduce additional zeros into the transfer function. the final overall fre - quency response takes on a band - pass characteristic, helping to reject noise outside of the intended nyquist zone. table 8 provides initial suggestions for prototyping purposes. some empirical optimization may be needed to help compensate for actual pcb p arasitics. layout consideration s the ADL5201 amplifier has two output pins for each polarity, and they are oriented in an alternating fashion. when designing the board, care should be taken to minimize the parasitic capacitance due to the routing that connects the corresponding outputs together. to minimize the parasitic capacitance, a good practice is to avoid any ground or power planes under this routing region and under the chokes. if the co mmon - mode load capacitance including the capaci - tance of the trace is > 2 pf, use parasitic suppressing resistors at the device output pins. the resistors should be placed in the output traces just after the crossover connections. use 5 ? series resistors (size 0402) to adequately de - q the output system without a significant decrease in gain. l6 50? ac 1:3 75? 75? 1h 5v 1h 5v cml c4 5v 1nf 1nf 1nf l1 l3 l5 l1 l3 l5 1nf digital interface ADL5201 c2 ad9246 ad9640 ad6655 09388-057 figure 58 . narrow - band if sampling solution for unbuffered adc applications table 8 . inte rface filter recommendations for various if sampling center frequencies center frequency (mhz) 1 db bandwidth (mhz) l1 (nh) c2 (pf) l3 ( nh) c4 (pf) l5 (nh) l6 (nh) 96 27 68 15 220 15 68 150 140 31 47 11 150 11 47 82 170 25 39 10 120 10 47 51 211 40 30 7 10 0 7 .5 30 43
data sheet ADL5201 rev. b | page 21 of 28 evaluation board the ADL5201 evaluation board is available with software to program the variable gain control. it is a 4 - layer board with a split ground plane for analog and digital sections. special care is taken to place the power decoupling capacitors close to the device pins. the board is designed for easy single - ended (through a mini - circuits tc3 - 1t+ rf transformer) or differential configuration for each channe l. evaluation board con trol software the ADL5201 evaluation board is configured with a usb - friendly interface to program the gain of the ADL5201 . the software graphical user interface ( see figure 59 ) lets users select a particular gain mode and gain level to write to the device . the gui also allows users to read back data from the sdio pin, showing the cur rently programmed gain setting. the s oftware setup files can be down loaded from the ADL5201 product page at www.analog.com . 09388-058 figure 59 . evaluation board control software
ADL5201 data sheet re v. b | page 22 of 28 schematics and artwo rk 09388-059 75? traces 50? traces remove plane under traces c17 1 3.3v 1 vxb 1 vxa 1 agnd 1 vpos r19 r20 r51 3 2 1 mode1 r2 r1 3 2 1 mode0 r6 5r 3 2 1 latch r8 r7 5432 1 pwrup 3 2 1 pwup r14 3 2 1 pm r15 5432 1 j1 r13 r12 r11 r10 r9 c1 5432 1 inb- r4 r3 r18 r17 3 2 1 a5 r16 c6 r21 c8 r22 r23 3 2 1 a4 r33 c16 r43 r46 3 2 1 a3 r32 c15 r38 r42 3 2 1 a2 r31 c14 r36 r37 3 2 1 a1 c13 r34 3 2 1 a0 r35 r30 r28 r27 np c2 c3 r47 5 4 3 2 5 4 3 2 outb? r29 c12 1 2 3 6 4 t1 r25 r26 c11 c10 r24 c7 c9 l2 22 21 24 23 18 16 17 2 3 12 11 7 8 19 20 pad 15 14 5 6 13 9 10 4 1 u1 l1 1 2 3 6 4 t2 pb1 pa7 pa6 pa5 pm latch mode0 mode1 1k? molex22-03-2031 1k? molex22-03-2031 1k? 1k? 3.3v red red molex22-03-2031 johnson142-0701-851 tbd0402 0? 0? 0 vpos 0 pb0 tbd0402 1k? molex22-03-2031 1k? 1k? pa1 3.3v 1k? pa2 1k? 1k? pa3 1k? pa4 1k? 1k? 1k? 1k? 3.3v vpos sclk/a4 gs1/cs/a3 gso/fa/a2 3.3v 3.3v 3.3v 3.3v 3.3v vpos 3.3v 3.3v 1k? 1k? 0? tcm3-1t+ 1k? 1k? tbd0402 tbd0402 0 0.1f tbd0402 tbd0402 0 10f 0.1f 0.1f 1h 0.1f molex22-03-2031 dni tbd0402 tbd0402 dni tbd0402 dni tbd0402 dni tbd0402 dni tbd0402 dni 1k? 1h 0.1f 0.1f 0? 0? dni tbd0402 tbd0402 tbd0402 dni tbd0402 tcm3-1t+ molex22-03-2031 molex22-03-2031 molex22-03-2031 tbd0402 0? dni dni tbd0402 dni tbd0402 dni tbd0402 red blk vpos 0.1f sido/a5 0.1f 0.1f 0.1f updn_dat/a0 pwup updn_clk/a1 3.3v pa0 molex22-03-2031 molex22-03-2031 yel agnd agnd agnd agnd updn_clk_a1 updn_dat_a0 pad vpos vpos_ig vpos_id pm pwup vout_neg vout_pos latch gs0_fa_a2 gs1_cs_n_a3 sclk_a4 sdio_a5 mode0 mode1 gnd_zap vin_neg vin_pos gnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd vout_pos vout_neg c4 c5 figure 60 . evaluation board schematic
data sheet ADL5201 rev. b | page 23 of 28 09388-060 figure 61 . logic schematic 09388-061 figure 62 . top layer 09388-062 figure 63 . bottom layer
ADL5201 data sheet re v. b | page 24 of 28 evaluation board con figuration options configuration options for the main section table 9 . bill of materials for main section components function default conditions c2 to c5, c7, c9, c17 po wer supply decoupling. nominal supply decoupling consists of a 0.1 f capacitor to ground. c2 = 10 f (size c7343) c3 to c 5 , c7, c9, c17 = 0.1 f (size 0603) u1 device under test. i nstalled inb ? t2 j1 c1 r3, r4, r9 to r 13 i nput interface. inb? is the rf input. t2 is a 3:1 impedance ratio balun used to transform a single ended 50 ? s ignal into a 150 ? b alanced differential signal. the input can be configured for a differential by removing r3 and installing a 0 ? j umper at r4. c 1 provides dc blocking . r12 and r13 are place holders and can be replaced with blocking capacitors when driving the ADL5201 from a fully differential source. r3 grounds one side of the differential drive interface for sing le - ended applications. r9, r10 , and r11 are provided for generic placement of matching components. t2 = tc3 - 1t+ (mini - circuits) c1 = 0.1 f (size 0 402 ) r3 , r12, r13 = 0 ? (size 0402) r4, r 9 to r11 = o pen inb ? (sma connector) installed j1 (sma connector) installed t1 c 10 to c 12 l1, l2 r19, r20, r 24 to r 28, r47, r48, r51 outb+, out b? o utput interface. t1 is a 3:1 impedance ratio balun used to transform a 150 ? b alance d differential signal to a 50 ? s ingled - end signal. c 10 and c11 are dc blocks. l1 and l2 provide dc bias to the open - collector output. r24 to r28 are provided for the generic placement of matching components. r47 grounds one side of the different ial outp ut interface for single - ended applications. t1 = tc3 - 1t+ (mini - circuits) c 10 to c 12 = 0.1 f (size 0 402 ) r 19 , r 20, r 24 to r 26, r47, r51 = 0 ? (size 0402) r27, r 28, r48 = open l1, l2 = 1 h (size 0805) out b + (sma connector) installed out b ? (sma connector) i nstalled p w u p, pwrup power - up interface. the ADL5201 is powered up by applying a logic high ( 1.4 v pw upa/b 3.3 v) to pwup from an external source or by insta lling a shunt between pin 1 an d p in 2 of the 3 - pin h eader, pwup . p wup (3 - pin header) installed pw r up (sma connector) installed a0 to a5 latch pm mode0, mode1 r1, r2, r5 to r8 , r14 to r1 8, r21 to r23 , r30 to r38 , r42, r43, r4 6 c6, c8, c13 to c16 gain control interface. all of the gain control functions are fully controlled via the usb microcontrolle r using the supplied software. three - pin headers allow for manual operation of the gain control , if desired. r 1, r2, r5 to r8, r14, r15, r17, r18 , r22, r23 , r34 to r38, r42, r43 , and r46 i solate the digital control pins from the microcontroller and provide current limiting. the r16, r21, and r30 to r33 resistors and the c6, c8, and c13 to c16 capacitors allow for the generic placement of filter components. a0 to a5 (3 -p in header) installed l atch (3 -pi n header) installed mode0 (3 -p in header) installed mode1 (3 - pin header) installed pm (3 - pin header) installed r1, r2, r5 to r8 , r14, r15, r17, r18, r22, r23, r34 to r38, r42, r43, r46 = 1 k ? (size 0402) r 16, r21, r30 to r33 = open c6, c8, c13 to c16 = open
data sheet ADL5201 rev. b | page 25 of 28 configuration options for the usb section table 10. bill of materials for usb section components default conditions c 31, c 62 22 pf (size 0603) c 49 1000 pf (size 0603) c2 8 to c3 0 , c 53 to c 55, c 57 to c61 0.1 f (size 0402) c 47, c 50 1 f (size 0402) c 52 , c5 6 10 pf (size 0402) d6 green led ( panasonic lnj308g8tra) j16 usb smt connector (hirose electric ux60a -mb - 5st 240- 0003 -4) r 39 , r 49 , r5 0 2 k? (s ize 0603) r 41 78.7 k? (size 0603) r 40 140 k? (size 0603) r 44 , r4 5 100 k? (size 0603) r 58 0 ? (size 0603) u6 usb microcontroller (cypress cy7c68013a - 56lfxc) u7 64 kbit eeprom (microchip 24lc64 - i/sn) u5 low dropout regulator (analog devices adp3334acpz ) y2 24 mhz crystal oscillator (ael crystals x24m000000s244)
ADL5201 data sheet rev. b | page 26 of 28 outline dimensions 0.50 bsc 0.50 0.40 0.30 0.30 0.25 0.18 compliant to jedec standards mo-220-wggd. 04-12-2012-a bottom view top view exposed pad p i n 1 i n d i c a t o r 4.10 4.00 sq 3.90 seating plane 0.80 0.75 0.70 0.20 ref 0.25 min coplanarity 0.08 pin 1 indi c ator 2.65 2.50 sq 2.45 1 24 7 12 13 18 19 6 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.05 max 0.02 nom figure 64. 24-lead lead frame chip scale package [lfcsp_wq] 4 mm 4 mm body, very very thin quad (cp-24-7) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ADL5201acpz-r7 ?40c to +85c 24 lead lfcsp_wq, 7 tape and reel cp-24-7 ADL5201-evalz evaluation board 1 z = rohs compliant part.
data sheet ADL5201 rev. b | page 27 of 28 notes
ADL5201 data sheet re v. b | page 28 of 28 notes ? 2011 - 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d09388 -0- 9/13(b)

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